AQA 8525 GCSE Computer Science · 3.4 Computer Systems

Stretch tasks Systems Architecture

Task 1

Quiz Challenge

A quiz game against four computer players, then short and long written answers.

  1. Quiz Blitz12 questions against the clock
  2. Quick Fire4 short answers
  3. Big Think2 long answers

About 20 minutes

Task 2

This or That

Pixel the cat asks 8 questions. Each has two answers: pick the right one.

  • Two answers to every question
  • A fish treat for every right answer
  • Streaks win Pixel shades, then a party hat

About 4 minutes

Task 3

Memory Match

Flip the cards two at a time to match each term card to its meaning card.

  • 12 cards: each term has a meaning
  • One peek at every card
  • Combo points for pairs found in a row

6 pairs, about 4 minutes

Task 4

Sort It

Sort each statement into the right box, like the tick-box tables in the exam.

  • 11 cards to sort into 3 boxes
  • Drag a card, tap a box or press its number
  • Combo points for cards sorted in a row

11 cards, about 4 minutes

The games need JavaScript. Every question is below, with the answers at the end.

Read the lesson: Systems Architecture

Systems Architecture: the questions

Quiz Challenge, round 1: Quiz Blitz

  1. What is the stored program concept?

    • Programs are wired into the hardware
    • Programs are stored inside the CPU only
    • Data is stored on paper
    • Instructions and data are held in the same memory
  2. What is the von Neumann bottleneck?

    • There are too many cores
    • Instructions and data compete for the same bus to memory
    • The CPU overheats
    • The hard drive fills up
  3. Which register holds the address of the next instruction?

    • Memory Data Register
    • Accumulator
    • Program Counter
    • Memory Address Register
  4. The Program Counter is incremented at the end of the cycle.

    • True
    • False
  5. Put the fetch stage in order.

    Number these 1 to 4.

    • The address goes out on the address bus
    • The instruction comes back on the data bus into the MDR
    • The address in the PC is copied into the MAR
    • The PC is incremented
  6. Which part of the CPU decodes the instruction?

    • The accumulator
    • The cache
    • The control unit
    • The ALU
  7. Why have clock speeds stopped climbing?

    • Programs cannot use faster clocks
    • Laws forbid it
    • RAM cannot be read any faster
    • Power use and heat rise faster than the speed
  8. Why is a quad core processor rarely four times faster?

    Tick 2.

    • Not all software splits its work across cores
    • Some tasks need each step's result before the next can start
    • The cores share one clock pulse
    • Cache is switched off on multi-core chips
    • Each core is slower than a single core
  9. Cache makes the processor itself faster.

    • True
    • False
  10. Why is there not more cache in a CPU?

    • It cannot store instructions
    • It wears out quickly
    • It is expensive per byte
    • It is slower than RAM
  11. Which of these is an embedded system?

    • A laptop
    • A desktop PC
    • A smartphone
    • A microwave's controller
  12. Which register holds the result of the most recent calculation?

Quiz Challenge, round 2: Quick Fire

  1. Explain why the Program Counter is incremented during the fetch stage, not at the end of the cycle. [2 marks]

  2. Explain why cache improves a processor's performance. [2 marks]

  3. Explain why an embedded system can be cheaper and more reliable than a general purpose computer. [2 marks]

  4. Describe what the MAR and the MDR hold during a fetch. [2 marks]

Quiz Challenge, round 3: Big Think

  1. Describe the fetch-decode-execute cycle, naming the registers and buses used. [6 marks]

  2. A gaming laptop has a 3.6 GHz quad core processor with 8 MB of cache. Explain how each of these features affects performance, and the limits of each. [6 marks]

This or That: tick the right answer

  1. Which register holds an address?

    • MDR
    • MAR
  2. Before von Neumann, how was a machine's job changed?

    • By installing an app
    • By rewiring it
  3. Where does the result of a calculation go?

    • The accumulator
    • The program counter
  4. Doubling the clock speed makes the heat...

    • Stay the same
    • Rise even faster
  5. Each step of a task needs the previous step's result. How much do extra cores help?

    • Very little
    • Four times over
  6. Why is cache fast?

    • It is stored on the hard drive
    • It is inside or very close to the CPU
  7. Which can never be repurposed?

    • A washing machine controller
    • A laptop
  8. What happens when a jump instruction is executed?

    • The MAR is cleared
    • A new address goes into the PC

Memory Match: match each term to its meaning

TermMeaning
A PC1 Instructions and data share memory
B MAR2 Result of the latest calculation
C MDR3 Address being read or written
D ACC4 Data just fetched, or about to be written
E Stored program concept5 Instructions and data compete for one bus
F Von Neumann bottleneck6 Address of the next instruction

Sort It: tick one box in each row

Clock speed, number of cores or cache?

StatementClock speedCoresCache
No help for tasks where each step needs the last
Holds recently used instructions close to the CPU
Measured in hertz
Cuts the time spent waiting for RAM
Each one is a complete processing unit
A quad core chip runs four instructions at once
Only helps if software splits the work
Heat and power rise faster than it does
One instruction stage happens per pulse
Expensive per byte, so there is little of it
3 GHz means three billion pulses a second
Answers

Round 1: Quiz Blitz

  1. Instructions and data are held in the same memory That is why one laptop can run any program without rewiring.
  2. Instructions and data compete for the same bus to memory The processor can spend much of its time waiting.
  3. Program Counter Its value is copied into the MAR at the start of the fetch.
  4. False It is incremented during the fetch, so it already points at the next instruction.
  5. The address in the PC is copied into the MAR → The PC is incremented → The address goes out on the address bus → The instruction comes back on the data bus into the MDR PC to MAR, increment, address bus out, data bus back.
  6. The control unit The control unit works out what operation is needed and what data it applies to.
  7. Power use and heat rise faster than the speed Beyond a point, the chip cannot be cooled.
  8. Not all software splits its work across cores; Some tasks need each step's result before the next can start Some work is inherently sequential, and much software is not written for many cores.
  9. False It reduces the time the processor spends waiting, so more instructions are completed per second.
  10. It is expensive per byte Cache is very fast, and very costly.
  11. A microwave's controller It is built into a larger device to do one dedicated task.
  12. accumulator The ALU puts its result in the accumulator.

Round 2: Quick Fire

    • So it already points at the next instruction
    • A jump writes a new address into the PC, which a later increment would spoil
    Model answer

    Incrementing during the fetch means the PC already points at the next instruction. If it waited until the end, a jump executed in this cycle would write a new address into the PC, only for the increment to overwrite it.

    • It holds recently and frequently used instructions and data close to the CPU
    • So the CPU spends less time waiting for RAM
    Model answer

    Cache holds recently and frequently used instructions and data inside or very close to the CPU, so the processor spends less time waiting for slow RAM and completes more instructions per second.

    • Its task is fixed, so it needs only a small processor, little memory and no full OS
    • With fewer, simpler parts, there is less to go wrong
    Model answer

    Its task is fixed, so it needs only a small processor, very little memory and no general purpose operating system. With fewer, simpler parts there is less to pay for and less to go wrong.

    • The MAR holds the address of the instruction being fetched
    • The MDR holds the instruction that comes back from memory
    Model answer

    The MAR holds the address of the instruction being fetched. The MDR holds the instruction that comes back from memory at that address.

Round 3: Big Think

    • The address in the PC is copied into the MAR
    • The PC is incremented
    • The address goes out on the address bus
    • The instruction comes back on the data bus into the MDR
    • The control unit decodes it
    • The ALU executes a calculation, with the result in the accumulator
    • A jump writes a new address into the PC
    • Then the cycle repeats
    Model answer

    The address in the PC is copied into the MAR, and the PC is incremented so it points at the next instruction. The address travels out along the address bus, and the instruction at that address comes back along the data bus into the MDR. The control unit decodes the instruction, working out what operation is needed. Then it is executed: a calculation is carried out by the ALU with the result in the accumulator, or a jump writes a new address into the PC. Then the cycle repeats, billions of times a second.

    • 3.6 GHz is 3.6 billion clock pulses per second
    • So more instructions are completed each second
    • But power use and heat rise faster than the speed
    • Four cores can run four instructions at the same instant
    • But only if the software splits the work, and some tasks are sequential
    • Cache cuts the time spent waiting for RAM
    • But cache is expensive per byte
    Model answer

    3.6 GHz means 3.6 billion clock pulses per second, so more instructions are completed each second, but power use and heat rise faster than the speed, which limits how high it can go. Four cores can execute four instructions at the same instant, but only if the software is written to split its work, and tasks where each step needs the previous result gain little. The 8 MB of cache keeps recently used data close to the CPU, so it spends less time waiting for RAM, but cache is expensive per byte, which is why there is not more of it.

This or That

  1. MAR The Address Register holds an address. The Data Register holds data.
  2. By rewiring it The stored program concept ended physical rewiring.
  3. The accumulator The PC holds the address of the next instruction.
  4. Rise even faster Heat and power climb faster than speed, which is why clock speeds stalled.
  5. Very little Sequential work cannot be split across cores.
  6. It is inside or very close to the CPU Fetching from cache takes a fraction of the time of fetching from RAM.
  7. A washing machine controller An embedded system is dedicated to one task.
  8. A new address goes into the PC The next fetch then starts from the new address.

Memory Match

  • A 6 PC: Address of the next instruction
  • B 3 MAR: Address being read or written
  • C 4 MDR: Data just fetched, or about to be written
  • D 2 ACC: Result of the latest calculation
  • E 1 Stored program concept: Instructions and data share memory
  • F 5 Von Neumann bottleneck: Instructions and data compete for one bus

Sort It

  1. Cores No help for tasks where each step needs the last Sequential work cannot be shared out.
  2. Cache Holds recently used instructions close to the CPU That is cache's job.
  3. Clock speed Measured in hertz Hertz means per second.
  4. Cache Cuts the time spent waiting for RAM Cache reduces waiting rather than speeding up the CPU.
  5. Cores Each one is a complete processing unit That is what a core is.
  6. Cores A quad core chip runs four instructions at once Each core works at the same instant.
  7. Cores Only helps if software splits the work Software must be written for many cores.
  8. Clock speed Heat and power rise faster than it does That is why clock speeds stopped climbing.
  9. Clock speed One instruction stage happens per pulse The clock sets the pace.
  10. Cache Expensive per byte, so there is little of it Cache is very fast and very costly.
  11. Clock speed 3 GHz means three billion pulses a second Clock speed counts pulses per second.