OCR J277 GCSE Computer Science · 1.1 Systems Architecture

Stretch tasks Architecture of the CPU

Task 1

Quiz Challenge

A quiz game against four computer players, then short and long written answers.

  1. Quiz Blitz12 questions against the clock
  2. Quick Fire4 short answers
  3. Big Think2 long answers

About 20 minutes

Task 2

This or That

Pixel the cat asks 8 questions. Each has two answers: pick the right one.

  • Two answers to every question
  • A fish treat for every right answer
  • Streaks win Pixel shades, then a party hat

About 4 minutes

Task 3

Memory Match

Flip the cards two at a time to match each term card to its meaning card.

  • 12 cards: each term has a meaning
  • One peek at every card
  • Combo points for pairs found in a row

6 pairs, about 4 minutes

Task 4

Sort It

Sort each statement into the right box, like the tick-box tables in the exam.

  • 12 cards to sort into 4 boxes
  • Drag a card, tap a box or press its number
  • Combo points for cards sorted in a row

12 cards, about 4 minutes

The games need JavaScript. Every question is below, with the answers at the end.

Read the lesson: Architecture of the CPU

Architecture of the CPU: the questions

Quiz Challenge, round 1: Quiz Blitz

  1. Which register holds the address of the next instruction to be fetched?

    • Memory Address Register
    • Memory Data Register
    • Accumulator
    • Program Counter
  2. The MAR holds the data that has just been fetched from memory.

    • True
    • False
  3. Which part of the CPU decodes instructions?

    • Accumulator
    • Control Unit
    • Arithmetic Logic Unit
    • Cache
  4. Put the fetch stage in order.

    Number these 1 to 4.

    • The address is sent along the address bus to memory
    • The instruction comes back along the data bus into the MDR
    • The address in the PC is copied into the MAR
    • The PC is incremented
  5. Which TWO are jobs of the ALU?

    Tick 2.

    • Adding two numbers
    • Comparing two values
    • Decoding instructions
    • Sending control signals
    • Holding the address of the next instruction
  6. Which bus carries memory addresses from the CPU to RAM?

    • Control bus
    • Address bus
    • Data bus
  7. Registers are faster to access than cache.

    • True
    • False
  8. Which register holds the result of a calculation carried out by the ALU?

  9. What is the key idea of the von Neumann architecture?

    • All data is stored inside the CPU
    • Programs are wired into the hardware
    • Instructions and data are stored in the same memory
    • Every instruction has its own processor
  10. Order these from fastest to slowest to access.

    Number these 1 to 4.

    • RAM
    • Registers
    • L1 cache
    • L3 cache
  11. During the fetch, which register receives the instruction sent back along the data bus?

    • MAR
    • PC
    • Accumulator
    • MDR
  12. What does a cache miss mean?

    • The instruction is skipped
    • The CPU has run out of registers
    • The data was not in cache, so it must come from RAM
    • The cache is full and has stopped working

Quiz Challenge, round 2: Quick Fire

  1. Describe the role of the Program Counter during the fetch stage. [2 marks]

  2. Explain the difference between the MAR and the MDR. [2 marks]

  3. Explain why a CPU with more cache can perform better. [2 marks]

  4. Describe the job of the ALU. [2 marks]

Quiz Challenge, round 3: Big Think

  1. Describe the fetch stage of the fetch-decode-execute cycle. Refer to the registers and buses used. [4 marks]

  2. Explain how the parts of the CPU work together to run a program. Refer to the ALU, the Control Unit, cache and registers. [6 marks]

This or That: tick the right answer

  1. Where are instructions kept in the von Neumann architecture?

    • In the same memory as data
    • In a separate memory from data
  2. Which is faster to reach?

    • A register
    • L1 cache
  3. During the fetch, when is the Program Counter incremented?

    • Once its address is copied to the MAR
    • At the very end of the cycle
  4. Which bus carries signals in both directions?

    • The data bus
    • The address bus
  5. What does more cache mainly do?

    • Cuts the time the CPU spends waiting
    • Raises the clock speed
  6. Where does the result of an ALU calculation go?

    • The program counter
    • The accumulator
  7. Which cache level is the smallest and fastest?

    • L3
    • L1
  8. The CPU looks in cache and the data it needs is not there. What is this called?

    • A cache hit
    • A cache miss

Memory Match: match each term to its meaning

TermMeaning
A PC1 Address being read from or written to
B MAR2 Data just fetched, or about to be written
C MDR3 One-way: carries addresses to memory
D Accumulator4 Address of the next instruction
E Address bus5 Two-way: carries instructions and values
F Data bus6 Result of an ALU calculation

Sort It: tick one box in each row

Which part of the CPU does each job?

StatementALUControl UnitCacheRegisters
The MAR and the MDR are two of these
Tiny stores inside the CPU that each hold a single value
Adds two numbers together
Carries out AND, OR and NOT operations
Cuts down the slow trips the CPU makes to RAM
Holds copies of data the CPU is likely to need again soon
Includes the program counter and the accumulator
Compares two values to see which is bigger
Decodes each instruction fetched from memory
Keeps every component in step with the clock
Sends control signals to the other components
Comes in levels called L1, L2 and L3
Answers

Round 1: Quiz Blitz

  1. Program Counter The PC points at the next instruction. Its address is copied into the MAR at the start of the fetch.
  2. False The MAR holds an address. The data or instruction fetched from that address arrives in the MDR.
  3. Control Unit The Control Unit works out what each instruction means, then sends control signals to carry it out.
  4. The address in the PC is copied into the MAR → The PC is incremented → The address is sent along the address bus to memory → The instruction comes back along the data bus into the MDR PC to MAR, increment the PC, address bus out to memory, then the instruction returns on the data bus to the MDR.
  5. Adding two numbers; Comparing two values The ALU does arithmetic and logic. Decoding and control signals belong to the Control Unit.
  6. Address bus The address bus is one-way: addresses only ever travel from the CPU out to memory.
  7. True Registers are part of the CPU itself, so they are the fastest storage in the whole computer.
  8. accumulator The accumulator (ACC) holds the results of the ALU's calculations.
  9. Instructions and data are stored in the same memory The stored program concept: instructions and data share one memory, and instructions are fetched one at a time.
  10. Registers → L1 cache → L3 cache → RAM Registers sit inside the CPU, L1 is on the core, L3 is shared between cores, and RAM is far slower than any cache.
  11. MDR The MDR holds the data or instruction that has just been fetched. MAR is the postcode, MDR is the parcel.
  12. The data was not in cache, so it must come from RAM On a miss the CPU has to go out to RAM, which is much slower than finding the data in cache.

Round 2: Quick Fire

    • It holds the address of the next instruction to be fetched
    • Its value is copied into the MAR
    • It is incremented to point at the following instruction
    Model answer

    The Program Counter holds the address of the next instruction. That address is copied into the MAR, and then the Program Counter is incremented so it points at the instruction after.

    • The MAR holds the address of the memory location being read from or written to
    • The MDR holds the data or instruction fetched from, or about to be written to, memory
    Model answer

    The MAR holds the address of the memory location being read from or written to. The MDR holds the data or instruction that has just been fetched from that location, or is about to be written to it.

    • More instructions and data can be held close to the CPU
    • So there are fewer slow trips to RAM, and less time spent waiting
    Model answer

    More cache means more frequently used instructions and data can be held close to the CPU, so there are fewer slow trips out to RAM and the CPU spends less time waiting.

    • It carries out arithmetic, such as addition and subtraction
    • It carries out logic, such as comparisons and AND, OR and NOT
    Model answer

    The ALU carries out all the arithmetic, such as addition and subtraction, and all the logic, such as comparing two values to see which is bigger.

Round 3: Big Think

    • The address in the PC is copied into the MAR
    • The PC is incremented
    • The address is sent to memory along the address bus
    • The instruction is sent back along the data bus
    • The instruction is placed in the MDR
    Model answer

    The address held in the Program Counter is copied into the MAR, and the Program Counter is incremented so it points at the next instruction. The address in the MAR is sent along the address bus to main memory. The instruction stored at that address is sent back along the data bus and placed in the MDR, ready to be decoded.

    • The Control Unit decodes instructions
    • The Control Unit sends control signals that coordinate the other parts
    • Everything is kept in step with the clock
    • The ALU carries out arithmetic
    • The ALU carries out logic and comparisons
    • Cache holds frequently used instructions and data close to the CPU
    • So the CPU makes fewer slow trips to RAM
    • Registers are tiny, very fast stores holding single values, such as the PC and the accumulator
    Model answer

    The Control Unit decodes each instruction and sends control signals to the other parts, keeping them in step with the clock. The ALU carries out the arithmetic, such as addition, and the logic, such as comparing two values. Cache holds copies of frequently used instructions and data close to the CPU, so there are fewer slow trips out to RAM. Registers are tiny, very fast stores that each hold a single value: the program counter holds the address of the next instruction and the accumulator holds the result from the ALU.

This or That

  1. In the same memory as data That is the stored program concept: instructions and data share one memory, and instructions are fetched one at a time.
  2. A register Registers are part of the CPU itself, so they beat even L1 cache.
  3. Once its address is copied to the MAR The PC goes up during the fetch, so it already points at the next instruction before this one is decoded.
  4. The data bus Data travels to and from memory, so the data bus is bidirectional. Addresses only go one way, from the CPU to memory.
  5. Cuts the time the CPU spends waiting Cache does not touch the clock speed. It means fewer slow trips to RAM, so more work is done each second.
  6. The accumulator The ACC holds results. The PC holds the address of the next instruction.
  7. L1 L1 sits on the core itself. L3 is the largest and slowest of the three, and it is shared between the cores.
  8. A cache miss A miss means a slower trip out to RAM. A hit means the data was already waiting in cache.

Memory Match

  • A 4 PC: Address of the next instruction
  • B 1 MAR: Address being read from or written to
  • C 2 MDR: Data just fetched, or about to be written
  • D 6 Accumulator: Result of an ALU calculation
  • E 3 Address bus: One-way: carries addresses to memory
  • F 5 Data bus: Two-way: carries instructions and values

Sort It

  1. Registers The MAR and the MDR are two of these The Memory Address Register and the Memory Data Register are both registers.
  2. Registers Tiny stores inside the CPU that each hold a single value Registers are the fastest storage in the computer, and each holds just one value.
  3. ALU Adds two numbers together Arithmetic, such as addition and subtraction, is the ALU's job.
  4. ALU Carries out AND, OR and NOT operations Boolean operations are logic, so they happen in the ALU.
  5. Cache Cuts down the slow trips the CPU makes to RAM Every cache hit is a trip to RAM the CPU does not have to make.
  6. Cache Holds copies of data the CPU is likely to need again soon Cache keeps recently and frequently used data close to the CPU.
  7. Registers Includes the program counter and the accumulator The PC and the ACC are registers: one holds the next address, the other holds results.
  8. ALU Compares two values to see which is bigger Comparisons are logic operations, and the ALU carries out all of the logic.
  9. Control Unit Decodes each instruction fetched from memory Working out what an instruction means is decoding, which the Control Unit does.
  10. Control Unit Keeps every component in step with the clock The Control Unit synchronises the components using the clock's pulses.
  11. Control Unit Sends control signals to the other components The Control Unit is the manager: its signals tell the other parts what to do and when.
  12. Cache Comes in levels called L1, L2 and L3 Cache is split into levels: L1 is the smallest and fastest, L3 the largest and slowest.