Structure and Function of the Processor

1 Describe the fetch stage of the fetch decode execute cycle, referring to the registers and buses involved. 5

One mark for each of the following, to a maximum of 5.

• The address in the Program Counter is copied to the MAR
• The Program Counter is incremented
• The address is placed on the address bus
• A read signal is sent on the control bus
• The instruction returns on the data bus into the MDR and is then copied to the CIR

Model answer. The address of the next instruction, held in the Program Counter, is copied into the Memory Address Register, and the Program Counter is then incremented so that it points at the following instruction. The address held in the MAR is placed on the address bus and a read signal is asserted on the control bus. Main memory responds by placing the contents of that location onto the data bus, from where it is loaded into the Memory Data Register. The instruction is then copied from the MDR into the Current Instruction Register, leaving the MDR free for any data the instruction subsequently requires.

2 Explain how a processor handles an interrupt. 5

One mark for each of the following, to a maximum of 5.

• Interrupts are checked at the end of each fetch decode execute cycle
• The priority of the interrupt is compared with that of the current task
• The contents of the registers are pushed onto a stack to save the current state
• The relevant interrupt service routine is loaded and executed
• Afterwards the saved state is popped back and execution resumes where it left off

Model answer. At the end of each fetch decode execute cycle the processor checks the interrupt register to see whether any interrupt has been raised. If one has, its priority is compared with that of the task currently executing, and if it is lower the interrupt is left pending. If it is higher, the processor saves its current state by pushing the contents of all its registers, including the Program Counter, onto a stack. The address of the appropriate interrupt service routine is then loaded into the Program Counter and that routine is executed. When it finishes, the saved register contents are popped from the stack and restored, so the interrupted program continues from exactly the point where it was suspended. Because a stack is used, an interrupt service routine can itself be interrupted by a higher priority interrupt and each state is restored in the correct reverse order.

3 Explain how pipelining improves processor performance and describe one situation in which its benefit is reduced. 5

One mark for each of the following, to a maximum of 5.

• Instructions are divided into stages such as fetch, decode and execute
• Different instructions occupy different stages at the same time
• Throughput approaches one instruction completed per cycle
• A conditional branch may mean the instructions already fetched are the wrong ones
• The pipeline must then be flushed, wasting the work already done

Model answer. Pipelining divides instruction processing into separate stages, typically fetch, decode and execute, and allows different instructions to occupy different stages at the same time. While one instruction is being executed, the next is being decoded and a third is being fetched, so although each individual instruction still takes three cycles to complete, one instruction finishes on every cycle once the pipeline is full, which raises throughput substantially without any increase in clock speed. The benefit is reduced when a conditional branch is encountered. The processor has already fetched and begun decoding the instructions that follow sequentially, but if the branch is taken those are not the instructions that should execute next. The pipeline must therefore be flushed and refilled from the branch target, discarding several cycles of completed work. Processors mitigate this using branch prediction, which guesses the likely outcome based on previous behaviour and speculatively fills the pipeline accordingly.

4 Compare the von Neumann and Harvard architectures. 6

One mark for each of the following, to a maximum of 6.

• Von Neumann uses a single memory for both instructions and data
• Harvard uses separate memories for instructions and data
• Von Neumann uses one set of buses, Harvard uses separate buses for each memory
• Harvard can fetch an instruction and data simultaneously, so it is faster
• Von Neumann suffers from the bottleneck of instructions and data competing for one bus
• Von Neumann is cheaper and simpler, Harvard is used in embedded and DSP systems

Model answer. The von Neumann architecture stores both instructions and data in a single shared memory, accessed through one set of address, data and control buses. The Harvard architecture uses physically separate memories for instructions and for data, each with its own set of buses. This leads directly to the key performance difference: in a Harvard system an instruction can be fetched at the same time as data is read or written, whereas in a von Neumann system both must use the same bus and therefore compete, producing what is known as the von Neumann bottleneck. The compensating advantages of von Neumann are cost and flexibility. Only one memory and one bus set are needed, which makes the hardware cheaper and simpler, and because instructions and data occupy the same memory the division between them can be varied freely, which suits general purpose computers running unpredictable workloads. Harvard architecture is more expensive and less flexible, since the split between instruction and data memory is fixed by the hardware, so it is used chiefly in embedded systems and digital signal processors where the program is fixed and predictable performance matters more. Many modern processors are hybrid, presenting a von Neumann model at the level of main memory while using separate instruction and data caches internally to gain the Harvard speed advantage.

5 Explain how the width of the address bus and the width of the data bus each affect the performance and capability of a processor. 4

One mark for each of the following, to a maximum of 4.

• The address bus width determines how many memory locations can be addressed
• An n bit address bus can address 2 to the power n locations
• The data bus width determines how much data is transferred in one operation
• A wider data bus increases throughput, so fewer transfers are needed for the same data

Model answer. The width of the address bus determines the size of the address space, because each line carries one bit of the address. An n bit address bus can therefore specify 2 to the power n distinct locations, which is why a 32 bit address bus limits a system to approximately 4 GB of addressable memory and why moving to 64 bit addressing was necessary. The width of the data bus determines how many bits are transferred between the processor and memory in a single operation. A 64 bit data bus moves eight bytes per transfer where a 32 bit bus moves four, so for the same volume of data half as many transfers are required, which directly increases throughput and reduces the time the processor spends waiting for memory.