Structure and Function of the Processor
The full fetch decode execute cycle with every register and bus, pipelining, and the architectures you must be able to compare at A Level depth.
Components and registers
The core components
| Component | Function |
|---|---|
| ALU | Performs all arithmetic and logical operations, and the shifts used in multiplication and division |
| Control Unit | Decodes instructions, generates control signals, synchronises components to the clock and directs data flow |
| Registers | Extremely fast storage inside the processor holding values currently in use |
| Cache | Small, very fast memory holding recently and frequently accessed instructions and data |
| Clock | Generates the regular pulse that synchronises all operations |
The registers you must know
| Register | Contents |
|---|---|
| PC Program Counter | Address of the next instruction to be fetched |
| MAR Memory Address Register | The address currently being read from or written to |
| MDR Memory Data Register | The data or instruction transferred to or from memory |
| CIR Current Instruction Register | The instruction currently being decoded and executed |
| ACC Accumulator | The result of ALU operations |
| Status register | Flags such as zero, negative, carry and overflow set by the last operation |
At GCSE the instruction sits in the MDR. At A Level it is copied from the MDR into the CIR so that the MDR is free for the data the instruction needs.
Buses
- Address bus. Unidirectional, carrying memory addresses from the processor. Its width determines the maximum addressable memory: an n bit address bus can address 2n locations.
- Data bus. Bidirectional, carrying data and instructions. Its width determines how much data moves per transfer, so a wider data bus increases throughput.
- Control bus. Bidirectional, carrying control signals such as read, write, clock, interrupt request and bus request.
A 32 bit address bus can address 232 locations, which is about 4 GB. This is precisely why 32 bit systems could not use more than 4 GB of RAM.
- The program counter holds the address of the next instruction.
- That address goes to memory along the address bus.
- The instruction comes back along the data bus and lands in the MDR.
- The control unit decodes it and works out what has to happen.
- The ALU executes it, and the program counter moves on by one.
The fetch decode execute cycle in full
Fetch
- The address in the PC is copied into the MAR.
- The PC is incremented.
- The address in the MAR is placed on the address bus and a read signal is sent on the control bus.
- The instruction at that address is returned on the data bus into the MDR.
- The instruction is copied from the MDR into the CIR.
Decode
- The Control Unit splits the instruction in the CIR into its opcode and operand.
- The opcode identifies the operation. The operand is the data or the address of the data.
- Control signals are generated for the units that will carry it out.
Execute
- The instruction is carried out: an ALU operation with the result in the accumulator, a transfer to or from memory, or a change to the PC in the case of a jump.
- The status register flags are updated.
The cycle then repeats.
Interrupts
An interrupt is a signal from a device or program requesting the processor's attention.
At the end of each cycle the processor checks the interrupt register. If an interrupt of higher priority than the current task is present:
- The contents of the registers are copied to a stack, saving the current state
- The relevant interrupt service routine is loaded and executed
- When it completes, the previous state is popped from the stack back into the registers
- Execution resumes exactly where it left off
Because a stack is used, interrupts can nest, so a higher priority interrupt can interrupt an interrupt service routine.
Learn the sequence, including that the check happens at the end of a cycle and that the stack is what makes nesting possible.
Step 1 of 7 Fetch: the address in the program counter is copied into the MAR.
Performance and architectures
Factors affecting performance
| Factor | Effect |
|---|---|
| Clock speed | More cycles per second means more instructions per second, but heat and power rise sharply |
| Number of cores | Genuine parallel execution, limited by whether software is multi threaded and by Amdahl's law |
| Cache size and levels | Higher hit rate means fewer slow accesses to main memory |
| Word length | Longer words mean more data processed per operation |
| Bus width | A wider data bus increases throughput, a wider address bus increases addressable memory |
Pipelining
Instructions are broken into stages, and while one instruction is being executed the next is being decoded and a third is being fetched.
Cycle 1: Fetch A Cycle 2: Fetch B Decode A Cycle 3: Fetch C Decode B Execute A Cycle 4: Fetch D Decode C Execute B
Throughput rises to roughly one instruction per cycle even though each instruction still takes three cycles.
The problem is branching. When a conditional jump is taken, the instructions already in the pipeline are wrong and must be discarded, which is a pipeline flush. Processors use branch prediction to guess which way a branch will go and reduce this cost.
Von Neumann against Harvard
| Von Neumann | Harvard | |
|---|---|---|
| Memory | One shared memory for instructions and data | Separate memories, and separate buses |
| Buses | One set, shared | Two sets, one for each memory |
| Speed | Slower, because instructions and data compete for the same bus, the von Neumann bottleneck | Faster, since an instruction and data can be fetched simultaneously |
| Cost and complexity | Cheaper and simpler | More expensive and more complex |
| Typical use | General purpose computers | Embedded systems and digital signal processors |
Many real processors are hybrid: von Neumann in main memory, Harvard at the cache level with separate instruction and data caches.
RISC against CISC
| RISC | CISC | |
|---|---|---|
| Instruction set | Small, simple instructions | Large, complex instructions |
| Instruction length | Fixed | Variable |
| Cycles per instruction | Usually one | Several |
| Instructions per task | More | Fewer |
| Pipelining | Straightforward, because instructions are uniform | Difficult, because instruction lengths vary |
| Complexity | In the compiler and the software | In the hardware |
| Power use | Lower | Higher |
| Examples | ARM | x86 |
The trade off is where the complexity sits. RISC pushes it into the compiler, CISC builds it into the hardware. RISC dominates mobile devices because of its power efficiency and its suitability for pipelining.
Co-processors and parallel systems
- A GPU has thousands of simple cores optimised for performing the same operation on large amounts of data at once, which suits graphics, machine learning and scientific simulation.
- Multicore systems run genuinely parallel threads.
- Parallel processing speeds up work only to the extent that the task can be divided. Amdahl's law states that the maximum speedup is limited by the fraction of the task that must remain sequential.
- Without a pipeline each instruction finishes fetch, decode and execute before the next one starts: 3 instructions take 9 cycles.
- With a pipeline the stages overlap, so while one instruction executes the next is decoded and the one after is fetched: 5 cycles.
- One instruction still takes 3 cycles. The gain is throughput. A taken branch flushes the pipeline, which is why branches are predicted.
Key terms you must be able to define
- ALU
- Arithmetic Logic Unit, performing all arithmetic and logical operations.
- Control Unit
- The component that decodes instructions and generates control signals to coordinate the processor.
- CIR
- Current Instruction Register, holding the instruction currently being decoded and executed.
- Status register
- A register holding flags such as zero, carry, negative and overflow set by the last operation.
- Opcode
- The part of an instruction identifying which operation to perform.
- Operand
- The part of an instruction giving the data or the address of the data to operate on.
- Interrupt
- A signal requesting the processor's attention, checked at the end of each cycle.
- Interrupt service routine
- The code executed in response to a particular interrupt.
- Pipelining
- Overlapping the fetch, decode and execute stages of consecutive instructions to increase throughput.
- Pipeline flush
- Discarding instructions already in the pipeline after a branch is taken.
- Von Neumann bottleneck
- The limit imposed by instructions and data sharing a single bus and memory.
- Harvard architecture
- An architecture with separate memories and buses for instructions and data.
- RISC
- Reduced Instruction Set Computer, using a small set of simple, uniform instructions.
- CISC
- Complex Instruction Set Computer, using a large set of powerful, variable length instructions.
- Amdahl's law
- The principle that speedup from parallelism is limited by the sequential fraction of a task.
Flashcards
Say the definition out loud before you flip the card. Retrieving it from memory is what builds recall, reading it again is not.
Reach the top grade on this topic
A Level answers on this topic must go beyond the GCSE version in three specific ways.
Include the CIR and the status register. A cycle description that stops at MDR is a GCSE answer. The instruction moves MDR to CIR, and the flags update on execute.
Explain the mechanism of the interrupt, including the stack. Registers are pushed to a stack, the ISR runs, the registers are popped back. The stack is what permits nesting, and saying so shows genuine understanding.
Quantify where you can. An n bit address bus addresses 2n locations. A 32 bit bus therefore reaches 4 GB, which explains a real historical limitation.
On comparisons, give the underlying cause. RISC pipelines well because its instructions are fixed length and take a uniform number of cycles. Harvard is faster because an instruction and its data can be fetched simultaneously rather than competing for one bus.
- Write the full ten step cycle from memory, naming every register and bus
- Describe the interrupt sequence including the stack and nesting
- Explain pipelining, the branching problem and branch prediction
- Compare RISC and CISC and Harvard and von Neumann with causes, not just properties
Mistakes that cost marks here
- Giving the GCSE five step cycle at A Level, with no CIR and no status register.
- Saying interrupts are checked continuously. They are checked at the end of each cycle.
- Omitting the stack from an interrupt answer, which loses the explanation of nesting.
- Saying RISC is 'simpler so faster'. It executes more instructions per task but pipelines far better.
- Confusing the address bus and data bus roles when explaining addressable memory.
Pipelining is why a modern processor completes roughly one instruction per cycle despite each instruction taking several cycles to finish. It is the same idea as a production line: nobody waits for the first car to be finished before starting the second.
Knowledge check
Exam-style questions
Five written questions in the style of the real paper. Write a full answer, then let the marker check it against the mark scheme.
- LThe address in the Program Counter is copied to the MAR
- LThe Program Counter is incremented
- LThe address is placed on the address bus
- LA read signal is sent on the control bus
- LThe instruction returns on the data bus into the MDR and is then copied to the CIR
The address of the next instruction, held in the Program Counter, is copied into the Memory Address Register, and the Program Counter is then incremented so that it points at the following instruction. The address held in the MAR is placed on the address bus and a read signal is asserted on the control bus. Main memory responds by placing the contents of that location onto the data bus, from where it is loaded into the Memory Data Register. The instruction is then copied from the MDR into the Current Instruction Register, leaving the MDR free for any data the instruction subsequently requires.
- LInterrupts are checked at the end of each fetch decode execute cycle
- LThe priority of the interrupt is compared with that of the current task
- LThe contents of the registers are pushed onto a stack to save the current state
- LThe relevant interrupt service routine is loaded and executed
- LAfterwards the saved state is popped back and execution resumes where it left off
At the end of each fetch decode execute cycle the processor checks the interrupt register to see whether any interrupt has been raised. If one has, its priority is compared with that of the task currently executing, and if it is lower the interrupt is left pending. If it is higher, the processor saves its current state by pushing the contents of all its registers, including the Program Counter, onto a stack. The address of the appropriate interrupt service routine is then loaded into the Program Counter and that routine is executed. When it finishes, the saved register contents are popped from the stack and restored, so the interrupted program continues from exactly the point where it was suspended. Because a stack is used, an interrupt service routine can itself be interrupted by a higher priority interrupt and each state is restored in the correct reverse order.
- LInstructions are divided into stages such as fetch, decode and execute
- LDifferent instructions occupy different stages at the same time
- LThroughput approaches one instruction completed per cycle
- LA conditional branch may mean the instructions already fetched are the wrong ones
- LThe pipeline must then be flushed, wasting the work already done
Pipelining divides instruction processing into separate stages, typically fetch, decode and execute, and allows different instructions to occupy different stages at the same time. While one instruction is being executed, the next is being decoded and a third is being fetched, so although each individual instruction still takes three cycles to complete, one instruction finishes on every cycle once the pipeline is full, which raises throughput substantially without any increase in clock speed. The benefit is reduced when a conditional branch is encountered. The processor has already fetched and begun decoding the instructions that follow sequentially, but if the branch is taken those are not the instructions that should execute next. The pipeline must therefore be flushed and refilled from the branch target, discarding several cycles of completed work. Processors mitigate this using branch prediction, which guesses the likely outcome based on previous behaviour and speculatively fills the pipeline accordingly.
- LVon Neumann uses a single memory for both instructions and data
- LHarvard uses separate memories for instructions and data
- LVon Neumann uses one set of buses, Harvard uses separate buses for each memory
- LHarvard can fetch an instruction and data simultaneously, so it is faster
- LVon Neumann suffers from the bottleneck of instructions and data competing for one bus
- LVon Neumann is cheaper and simpler, Harvard is used in embedded and DSP systems
The von Neumann architecture stores both instructions and data in a single shared memory, accessed through one set of address, data and control buses. The Harvard architecture uses physically separate memories for instructions and for data, each with its own set of buses. This leads directly to the key performance difference: in a Harvard system an instruction can be fetched at the same time as data is read or written, whereas in a von Neumann system both must use the same bus and therefore compete, producing what is known as the von Neumann bottleneck. The compensating advantages of von Neumann are cost and flexibility. Only one memory and one bus set are needed, which makes the hardware cheaper and simpler, and because instructions and data occupy the same memory the division between them can be varied freely, which suits general purpose computers running unpredictable workloads. Harvard architecture is more expensive and less flexible, since the split between instruction and data memory is fixed by the hardware, so it is used chiefly in embedded systems and digital signal processors where the program is fixed and predictable performance matters more. Many modern processors are hybrid, presenting a von Neumann model at the level of main memory while using separate instruction and data caches internally to gain the Harvard speed advantage.
- LThe address bus width determines how many memory locations can be addressed
- LAn n bit address bus can address 2 to the power n locations
- LThe data bus width determines how much data is transferred in one operation
- LA wider data bus increases throughput, so fewer transfers are needed for the same data
The width of the address bus determines the size of the address space, because each line carries one bit of the address. An n bit address bus can therefore specify 2 to the power n distinct locations, which is why a 32 bit address bus limits a system to approximately 4 GB of addressable memory and why moving to 64 bit addressing was necessary. The width of the data bus determines how many bits are transferred between the processor and memory in a single operation. A 64 bit data bus moves eight bytes per transfer where a 32 bit bus moves four, so for the same volume of data half as many transfers are required, which directly increases throughput and reduces the time the processor spends waiting for memory.