Types of Processor
RISC against CISC in the depth the specification demands, GPUs, multicore and parallel systems, and how to compare them in an exam.
RISC and CISC
The central question is where the complexity sits: in the hardware, or in the compiler.
CISC, Complex Instruction Set Computer
- A large instruction set with powerful, specialised instructions
- Instructions are of variable length and take varying numbers of cycles
- One instruction may perform what would otherwise take several
- Complexity is built into the hardware, often using microcode to break complex instructions into internal steps
- Fewer instructions are needed per task, so programs are shorter, which mattered enormously when memory was scarce
- Harder to pipeline, since instruction lengths and durations vary
- Example: the x86 family in desktop and laptop computers
RISC, Reduced Instruction Set Computer
- A small instruction set of simple operations
- Instructions are of fixed length and typically execute in one cycle
- More instructions are needed per task, so programs are longer
- Complexity is moved into the compiler, which must build complex operations from simple ones
- Pipelines extremely well, because every instruction takes the same shape and duration
- Lower power consumption and simpler hardware
- Example: ARM, used in virtually all mobile devices
| RISC | CISC | |
|---|---|---|
| Instruction set size | Small | Large |
| Instruction length | Fixed | Variable |
| Cycles per instruction | Usually one | Several |
| Instructions per program | More | Fewer |
| Complexity is in | The compiler | The hardware |
| Pipelining | Straightforward | Difficult |
| Power consumption | Lower | Higher |
| Registers | Many | Fewer |
Fixed length instructions pipeline cleanly, and simpler hardware draws less power. On a device running from a battery, power efficiency outweighs everything else.
- RISC does the job with four simple instructions, one cycle each.
- CISC does it with one complex instruction that takes several cycles.
- The trade off is where the complexity sits: RISC puts it in the compiler, CISC in the hardware.
GPUs and parallel systems
Graphics Processing Units
A GPU contains thousands of relatively simple cores designed to perform the same operation on many data items simultaneously. This is single instruction, multiple data, or SIMD.
Well suited to:
- Graphics rendering, where the same lighting calculation applies to millions of pixels
- Machine learning, which is dominated by matrix multiplication
- Scientific simulation, image and video processing
- Cryptographic work and password cracking
Poorly suited to:
- Tasks with complex branching, where different data items need different code paths
- Sequential tasks where each step depends on the previous result
- General purpose operating system work
A CPU has few powerful cores optimised for complex sequential work with sophisticated branch prediction. A GPU has many simple cores optimised for throughput on uniform work. They are complementary, not competing.
Multicore and parallel systems
- Multicore. Several complete processing units on one chip, each able to execute a separate thread.
- Parallel processing. Dividing a task so that parts run simultaneously on different processors.
Limits on parallel speedup:
- Amdahl's law. If a fraction of the task must remain sequential, that fraction sets a ceiling on the possible speedup no matter how many processors are added.
- Data dependencies. A step that needs the result of a previous step cannot start early.
- Communication overhead. Coordinating processors and sharing data costs time that grows with the number of processors.
- Software support. Code that is not written to be multi threaded uses one core.
"Explain why doubling the number of cores does not halve the execution time." The answer needs Amdahl's law, data dependencies, coordination overhead and software support, not just one of them.
- One core takes the jobs one after another, in order.
- Four cores take four jobs at once, so the queue clears sooner.
- Only if the work can be split. Some jobs must wait for the one before.
- A GPU takes this much further: thousands of tiny cores, one kind of job.
Key terms you must be able to define
- RISC
- Reduced Instruction Set Computer, using few simple fixed length instructions.
- CISC
- Complex Instruction Set Computer, using many complex variable length instructions.
- Microcode
- Low level instructions inside a CISC processor that implement its complex instructions.
- GPU
- Graphics Processing Unit, with many simple cores optimised for the same operation on much data.
- SIMD
- Single Instruction Multiple Data, applying one operation across many data items simultaneously.
- Multicore
- A processor containing several complete cores capable of independent execution.
- Parallel processing
- Dividing a task so that parts execute simultaneously on different processors.
- Amdahl's law
- The principle that speedup is limited by the fraction of a task that must be sequential.
- Co-processor
- A secondary processor handling specific tasks to relieve the main processor.
Flashcards
Say the definition out loud before you flip the card. Retrieving it from memory is what builds recall, reading it again is not.
Reach the top grade on this topic
- Explain RISC and CISC as a trade off about where complexity sits, not as good against bad
- Link RISC's fixed length instructions directly to its suitability for pipelining
- Explain GPU suitability in terms of the same operation applied to many data items
- Give at least three separate reasons why parallel speedup is less than linear
- Name a real example of each architecture: ARM for RISC, x86 for CISC
Mistakes that cost marks here
- Saying RISC is faster than CISC. It uses more instructions per task but pipelines far better.
- Saying a GPU is simply a faster processor. It is optimised for throughput on uniform work, not for sequential complexity.
- Giving only Amdahl's law when asked why parallelism does not scale linearly.
- Forgetting that most CISC processors now translate instructions into RISC style operations internally.
The ARM architecture that powers almost every phone was designed by a small team in Cambridge in the 1980s. Its low power consumption was originally an accident of the design, not a goal, and it turned out to be the single most valuable property a processor could have.
Knowledge check
Exam-style questions
Five written questions in the style of the real paper. Write a full answer, then let the marker check it against the mark scheme.
- LRISC has a small instruction set with fixed length instructions, CISC has a large set with variable length
- LRISC instructions usually take one cycle, CISC instructions take several
A RISC processor has a small instruction set consisting of simple, fixed length instructions, whereas a CISC processor has a large instruction set containing complex instructions of variable length. As a consequence, RISC instructions typically complete in a single clock cycle while CISC instructions may take several, which means a RISC program needs more instructions to accomplish the same task but is far easier to pipeline.
- LSimpler hardware consumes less power
- LBattery life is a critical constraint on a mobile device
- LFixed length uniform instructions pipeline effectively, giving good throughput
- LLess complex hardware also generates less heat, which matters in a sealed device
RISC processors use a small set of simple instructions implemented in comparatively simple hardware, and that simplicity translates directly into lower power consumption per instruction. On a mobile device, where everything runs from a battery of fixed capacity, power efficiency is the dominant design constraint and outweighs raw peak performance. The uniform, fixed length instructions also pipeline extremely effectively, so despite each instruction doing less work the processor achieves high throughput, closing much of the performance gap. Finally, simpler hardware drawing less power generates less heat, which is essential in a thin sealed device with no fan and no room for a heatsink.
- LTraining is dominated by the same arithmetic applied to very large amounts of data
- LA GPU has thousands of simple cores that operate in parallel
- LThis matches the SIMD model of one instruction applied to many data items
- LA CPU has few cores optimised for complex sequential work, so it processes far fewer values per cycle
Training a machine learning model consists overwhelmingly of matrix multiplication, which means the same arithmetic operation applied independently to enormous numbers of values. A GPU is built for exactly this: it contains thousands of relatively simple cores that all execute the same instruction on different data at the same time, which is the single instruction multiple data model. Because the calculations for different elements do not depend on one another, they can all proceed in parallel with almost no coordination cost, so a GPU can complete in one pass what would take a CPU many thousands. A CPU has only a handful of cores, each of which is optimised for complex sequential work with sophisticated branch prediction and large caches, so although each core is individually far more capable, the total number of arithmetic operations completed per cycle is orders of magnitude lower for this kind of workload.
- LPart of the task must be executed sequentially and cannot be divided
- LAmdahl's law limits the speedup to the fraction that can be parallelised
- LData dependencies mean some steps must wait for earlier results
- LCoordinating the cores and sharing data adds overhead
- LThe software may not divide the work evenly, leaving some cores idle
Only part of a program can usually be parallelised. Any section that must execute sequentially, such as reading the input, setting up data structures or producing the final output, takes exactly the same time regardless of how many cores are available, and Amdahl's law states that this sequential fraction places a hard ceiling on the achievable speedup. Within the parallel section, data dependencies further limit what can genuinely run at once, because a calculation that requires the result of an earlier step cannot begin until that step has completed. On top of this, running work across four cores introduces overhead that did not exist with one: threads must be created and scheduled, access to shared data must be synchronised to prevent corruption, and results must be gathered and combined at the end, all of which consumes time that grows as more cores are added. Finally, the work may not divide into four equal parts, so some cores finish early and sit idle while the slowest thread completes, and the overall time is determined by that slowest thread rather than by the average.
- LA secondary processor that handles specific tasks
- LIt relieves the main processor of that work
- LGives a valid example such as a GPU or a maths co-processor
A co-processor is an additional processor that works alongside the main CPU and is specialised for a particular class of task, taking that work off the CPU so it is free to do other things. Because it is designed for one kind of computation it can perform that work far more efficiently than a general purpose processor would. The most familiar example is a GPU, which handles the rendering calculations for graphics and, increasingly, the matrix arithmetic for machine learning, allowing the CPU to run the operating system and application logic without being blocked by that work.